1. Field of the Invention
The present invention relates to a memory module and a memory system, and more particularly to a memory module having a matching capacitor and a memory system having the same.
2. Description of the Related Art
The speed of data transmission between semiconductor memory devices and memory controllers is continuously being increased. As the operating speed of memory systems increases, the signal integrity (SI) of signals transmitted and received between the memory modules and the respective memory controllers degrades. Accordingly, various attempts have been made to solve the degradation of signal integrity (SI).
FIG. 1 is a schematic diagram illustrating a conventional memory system.
Referring to FIG. 1, the memory system includes a memory controller 10, memory modules 20 and 30, and sockets 40 and 50 for coupling the memory controller 10 to the memory modules 20 and 30.
The memory modules 20 and 30 are electrically coupled to the sockets 40 and 50 through tabs (not shown) mounted on a board of the memory module. The memory modules 20 and 30 each include dynamic random access memory (DRAM) 22 and 32. The memory controller 10 is coupled to the sockets 40 and 50 through a main bus MBUS, and the sockets 40 and 50 are coupled to each of the data pins DQ (not shown) of the DRAMs 22 and 32 in the memory modules 20 and 30 through data buses DBUS1 and DBUS2. The data buses DBUS1 and DBUS2 that electrically couple the main bus MBUS to each of the DRAMs 22 and 32 include stub resistors 24 and 34 so as to improve the signal integrity (SI).
FIG. 2A is a schematic diagram illustrating a channel topology for measuring a degree of impedance matching of the memory-system shown in FIG. 1 when the DRAM 22 in the memory module 20 operates in a read/write operation mode, and the DRAM 32 in the memory module 30 operates in on-die termination (ODT) mode.
FIG. 2B is a smith chart illustrating the impedance viewed at port P11 shown in FIG. 2A. The smith chart shown in FIG. 2B shows a simulation result in a case where the stub resistors 24 and 34 have a resistance value of about 20Ω, respectively, ODT resistors included in the DRAMs 22 and 32 have a resistance value of about 50Ω, and the data buses DBUS1 and DBUS2 have a resistance value of about 60Ω, respectively. Referring to the smith chart shown in FIG. 2B, impedance in the read/write operation mode of the memory system at high frequency operation is considerably distant from a matching point.
FIG. 3A is a schematic diagram illustrating a channel topology for measuring a degree of impedance matching of the memory system shown in FIG. 1 when the DRAM 22 in the memory module 20 operates in the read/write mode, and the DRAM 32 in the memory module 30 operates in on-die termination (ODT) mode.
FIG. 3B is a smith chart illustrating the impedance viewed at port P12 shown in FIG. 3A. Referring to the smith chart shown in FIG. 3B, impedance in the ODT mode of the memory system at high frequency operation is considerably distant from a matching point.
As described above, in order to improve the signal integrity (SI), the conventional memory system includes stub resistors coupled to each of the data buses of the memory modules; however, impedance mismatching is still present due to the impedance of the data buses DBUS1 and DBUS2, and the semiconductor memory devices i.e., DRAMs 22 and 32.
Korean Patent Publication No. 10-0228148 discloses an impedance matching technique between memory modules by employing an impedance matching circuit having a capacitor positioned between a raw address strobe (RAS) pin and a tab mounted on the memory module.